Virtual channel DRAM

专利摘要:
In the virtual channel DRAM of the present invention, data can be transferred between one of the channels and a number of the segments in such a way to reduce test time for a whole chip. The virtual channel DRAM includes: a number of segments for dividing a cell conducted to bit line by an active command is divided into a number blocks; a number of segment selecting units for selectively conducting the bit line in one of the segments to a data transfer line; a number of channels for temporarily storing data transferred among the bit line, the data transfer line and a channel bus line; a number of channel selecting units for selectively conducting the channel bus line in one of the channels to the data transfer line; and a control signal generating unit for generating a first control signal used for selectively conducting the bit line in one of the segments to the data transfer line and used for simultaneously conducting the bit lines of all segments to the data transfer line in a predetermined external command mode.
公开号:US20010005373A1
申请号:US09/727,586
申请日:2000-12-04
公开日:2001-06-28
发明作者:Dae-Sik Song
申请人:Hyundai Electronics Industries Co Ltd；
IPC主号:G11C11-4094

专利说明:
[0001] The present invention relates to a virtual channel DRAM; and, more particularly, to a virtual channel DRAM capable of reducing test time for an entire chip by providing data transfer between a channel and a number of segment blocks all with a predetermined command mode. [0001] PRIOR ART OF THE INVENTION
[0002] FIG. 1 is a diagram for explaining data transfer between segments and channels in a conventional virtual channel DRAM. [0002]
[0003] A segment is a unit for dividing whole cells, that are conducted to bit line pair BL/BLB by an active command, into a number of blocks. A channel refers to a register for storing data of a whole or some part, of the cell, that are conducted to the bit line pair BL/BLB by the active command. In the virtual channel DRAM, the number of total bits of the segment is identical that of the channel so that data transfer is performed between one of segments and one of channels. [0003]
[0004] FIG. 2 is a diagram of conventional segments [0004] 10_0 to 10_N shown in FIG. 1, that is the unit for dividing whole cells that are conducted to the bit line pair BL/BLB by the active command into, a number of blocks.
[0005] FIG. 3 is a diagram of a conventional segment selector [0005] 20 shown in FIG. 1, that selectively conducts bit line BL/BLB bus in one of the segments 10_0 to 10_N. As shown in FIG. 3, in the segment selector 20, a NMOS transistor is coupled respectively between each bit line pair BL/BLB and each data transfer line and switched by an SGS<N> signal.
[0006] The SGS<[0006] 0> among SGS<0>, . . . , SGS<N> transits to logic high when bit line pair BL/BLB bus of a segment<0> block is conducted to the data transfer line. And the SGS<N> transits to logic high when bit line pair BL/BLB bus of a segment<N> block is conducted to the data transfer line.
[0007] FIG. 4 is a diagram of a conventional channel selector [0007] 40 shown in FIG. 1, that selectively conducting CRG/CRGB bus in one of a number of channels to the data transfer line. As shown in FIG. 4, in the segment selector 40, a NMOS transistor is coupled between each CRG/CRGB bus line and each data transfer line, respectively, and switched by a CS<M> signal.
[0008] The CS<[0008] 0> among CS<0>, . . . , CS<N> transits to logic high when CRG/CRGB bus of a channel<0> channel is conducted to the data transfer line. And the CS<M> transits to logic high when CRG/CRGB bus of a channel<M> channel is conducted to the data transfer line.
[0009] FIG. 5 is a diagram of conventional channels [0009] 50_0 to 50_N shown in FIG. 1, that stores temporarily data transferred among the bit line pair BL/BLB bus, the data transfer line and the channel bus lines CRG, CRGB.
[0010] FIG. 6 is a circuit diagram of an SGS signal generator [0010] 30 shown in FIG. 1, that generates control signals SGS<0>, . . . , SGS<N> for selectively conducting bit line pair BL/BLB in one of a number of segments and the data transfer line;
[0011] The conventional SGS signal generator [0011] 30 includes: NAND gates NA0, NA2, . . . , to each of which SAB<0>, SAB<1>, . . . , SAB<K> are applied; inverters INV0, INV2, . . . , for inverting outputs of the NAND gates NA0, NA2, . . . , to provide SGS<0>, SGS<2>, . . . ; NAND gates NA1, NA3, . . . , to each of which SA<0>, SAB<1>, . . . , SAB<K>; and inverters INV1, INV3, . . . , for inverting outputs of the NAND gates NA1, NA3, . . . , to provide SGS<1>, SGS<3>, . . .
[0012] Here, the SA<[0012] 0>, SAB<0>, SA<1>, SAB<1>, . . . , SA<N>, SAB<N> signals are address signals applied from external for selecting the segment. The SA<0> becomes logic high when the address signal determining logic of SA<0> and SAB<0> among the address signals is logic high. On the contrary, the SAB<0> becomes logic high when the address signal determining logic of SA<0> and SAB<0> among the address signals logic low.
[0013] The SA<K> becomes logic high when the address signal determining logic of SA<K> and SAB<K> among the address signals is logic high. On the contrary, the SAB<K> becomes logic high when the address signal determining logic of SA<K> and SAB<K> among the address signals is logic low. [0013]
[0014] The SGS<[0014] 0> that becomes logic high when the bit line BL/BLB bus of the segment<0> block is conducted to the data transfer line becomes logic high when the SAB<0>, SAB<1>, . . . , SAB<K> signals become logic high. And the SGS<N> that becomes logic high when the bit line BL/BLB bus of the segment<N> block is conducted to the data transfer line becomes logic high when the SA<0>, SA<1>, . . . , SA<K> signals become logic high.
[0015] A BGM signal becomes logic high when a command for data transfer between the segment and the channel is applied. [0015]
[0016] However, in data transfer between the segments and the channels in the conventional virtual channel DRAM, one of the segments always corresponds to one of the channels. Therefore, the command for data transfer from the channel to the segment should be inputted N times to transfer data from one of the channels to N segments. [0016] SUMMARY OF THE INVENTION
[0017] Therefore, it is an object of the present invention to provide a virtual channel DRAM capable of reducing chip test time by configuring logic in such a way to simultaneously transfer data from a channel to N segments with a predetermined external command input. [0017]
[0018] In accordance with an aspect of the present invention, there is provided a virtual channel DRAM comprising; a number of segments for dividing a cell conducted to bit line by an active command is divided into a number blocks; a number of segment selecting units for selectively conducting the bit line in one of the segments to a data transfer line; a number of channels for temporarily storing data transferred among the bit line, the data transfer line and a channel bus line; a number of channel selecting units for selectively conducting the channel bus line in one of the channels to the data transfer line; and a control signal generating unit for generating a first control signal used for selectively conducting the bit line in one of the segments to the data transfer line and used for simultaneously conducting the bit lines of all segments to the data transfer line in a predetermined external command mode. [0018]
[0019] The control signal generating unit includes: even order NAND gates at input stage, to each of which address signals applied from external to select one of the segments and a second control signal; odd order NABD gates at input stage, to each of which the address signals applied from external to select one of the segments and the second control signal; even order NAND gates at output stage, to each of which outputs of the even order NAND gates at the input stage and a third control signal and each of which provides the first control signal; and odd order NAND gates at output stage, to each of which outputs of the odd order NAND gates at the input stage and the third control signal and each of which provides the first control signal. [0019]
[0020] The second control signal becomes logic high when a command corresponding to data transfer between the segments and the channels is applied. [0020]
[0021] The third control signal becomes logic high in an external command mode for a predetermined test in which data is transferred from the channels to the segments. [0021]
[0022] In accordance with another aspect of the present invention, there is provided a virtual channel DRAM comprising; a number of segments for dividing a cell conducted to a bit line by an active command into a number of blocks; a segment selecting unit for selectively conducting the bit line in one of the segments to a data transfer line and for selectively conducting the bit lines in all segments to the data transfer line in a predetermined external command mode; a number of channels for temporarily storing data transferred among the bit line, the data transfer line and a channel bus line; a number of channel selecting units for selectively conducting the channel bus line in one of the channels to the data transfer line; and a control signal generating unit for generating a control signal for selectively conducting the bit line in one of the segments to the data transfer line. [0022]
[0023] The segment selecting unit includes transfer gates, each coupled between the bit line of each segment and the data transfer line and switched by the control signal selecting one of the segments and a signal, wherein the signal being logic high in an external command mode for a predetermined test in which data should be transferred from the channels to the segments. The transfer gates can be implemented with NMOS transistors. [0023] BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The above and other objects and features of the instant invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which: [0024]
[0025] FIG. 1 is a diagram for explaining data transfer between segments and channels in a conventional virtual channel DRAM; [0025]
[0026] FIG. 2 is a diagram of a conventional segment shown in FIG. 1; [0026]
[0027] FIG. 3 is a diagram of a conventional segment selector shown in FIG. 1; [0027]
[0028] FIG. 4 is a diagram of a conventional channel selector shown in FIG. 1; [0028]
[0029] FIG. 5 is a diagram of a conventional channel shown in FIG. 1; [0029]
[0030] FIG. 6 is a circuit diagram of an SGS signal generator [0030] 30 shown in FIG. 1;
[0031] FIG. 7 is a diagram for explaining data transfer between segments and channels in a virtual channel DRAM of the present invention; [0031]
[0032] FIG. 8 is a circuit diagram of an NSGS signal generator shown in FIG. 7; [0032]
[0033] FIG. 9 is a diagram for explaining another embodiment of data transfer between segments and channels in the virtual channel DRAM of the present invention; and [0033]
[0034] FIG. 10 is a diagram of an embodiment of a segment selector [0034] 120 shown in FIG. 9. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0035] In the accompanying drawings, elements having identical functions are referred as an identical reference notation and, for the sake of simplicity, repeated description for each of them will be omitted. [0035]
[0036] FIG. 7 is a diagram for explaining data transfer between segments and channels in a virtual channel DRAM of the present invention. FIG. 7 is similar to FIG. 1 except that an NSGS control signal generator [0036] 130 replaces the SGS control signal generator 30. The NSGS control signal generator 130 generates a control signal for simultaneously conducting bit lines BL, BLB of a number of segments 10_0-10_N to a data transfer line with a predetermined external command.
[0037] And, in FIG. 7, a number of the segments [0037] 10_0 to 10_N for dividing the whole cell conducted to the bit lines BL, BLB by the active command into a number of blocks are as similar to those as shown in FIG. 2.
[0038] And, in FIG. 7, a plurality of segment selector [0038] 20 for selectively conducting the bit lines BL, BLB in one of the segments 10_0-10_N to the data transfer line are similar to those as shown in FIG. 3.
[0039] The SGS<[0039] 0> among the SGS<0>, . . . , SGS<N> becomes logic high when the bit line pair BL, BLB bus of a segment<0> block are conducted to the data transfer line. And the SGS<0>, . . . SGS<N> signals simultaneously are make logic high by the external command mode so that the bit line pair BL, BLB bus of all the segments are conducted to the data transfer line, simultaneously.
[0040] And, in FIG. 7, the plurality of channel selectors [0040] 40 for selectively conducting CRG/CRGB bus in one of the channels to the data transfer line are similar to those as shown in FIG. 4. A CS<0> among the CS<0> to CS<M> becomes logic high when CRG/CRGB bus of channel<0> is conducted to the data transfer line and CS<M> becomes logic high when CRG/CRGB bus of channel<M> is conducted to the data transfer line.
[0041] And, in FIG. 7, a number of channels [0041] 50_0 to 50_N temporarily storing data transferred between the bit line BL, BLB, the data transfer line and channel bus lines CRG/CRGB are similar to those as shown in FIG. 5.
[0042] FIG. 8 is a circuit diagram of an NSGS signal generator [0042] 130 shown in FIG. 7. The NSGS signal generator 130 selectively conducts bit line pair BL/BLB bus in one of the segments to the data transfer line or selectively conducts the bit line pair BL/BLB bus in the segments to the data transfer line in the predetermined external command mode, simultaneously.
[0043] The NSGS signal generator [0043] 130 includes: NAND gates NA0, NA2, . . . , to each of which the SAB<0>, SAB<1>, . .. , SAB<K> and the BGM signals are applied; NAND gates NA0_0, NA0_2, . . . , to each of which outputs of the even order NAND gates NA0, NA2, . . . and the inverted RTM signal are applied; NAND gates NA1, NA3, . . . , to each of which the SA<0>, SA<1>, . . . , SAB<1>, SAB<2>, . . . , and the BGM signals are applied; and NAND gates NA0_1, NA0_3, . . . , to each of which outputs of the odd order NAND gates NA1, NA3, . . . and the inverted RTM signal are applied to provide the SGS<1>, SGS<3>, . . .
[0044] The SA<[0044] 0>, SAB<0>, SA<1>, SAB<1>, . . . , SA<N>, SAB<N> signals are address signals applied from external for selecting the segment. The SA<0> becomes logic high when the address signal determining logic of the SA<0> and the SAB<0> among the address signals is logic high. On the contrary, the SAB<0> becomes logic high when the address signal determining logic of the SA<0> and the SAB<0> among the address signals is logic low.
[0045] The SA<K> becomes logic high when the address signal determining logic of the SA<K> and the SAB<K> among the address signals is logic high. On the contrary, the SAB<K> becomes logic high when the address signal determining logic of the SA<K> and the SAB<K> among the address signals is logic low. [0045]
[0046] An SGS<[0046] 0> signal that becomes logic high when the bit lines BL/BLB bus of the segment <0> block is conducted to the data transfer line becomes logic high when the SAB<0>, SAB<1>, . . . , SAB<K> signals become logic high. And an SGS<N> that becomes logic high when the bit lines BL/BLB bus of the segment <N> block is conducted to the data transfer line becomes logic high when the SA<0>, SA<1>, . . . , SA<K> signals become logic high.
[0047] An RTM signal becomes logic high in an external command mode for a particular test in which data should be transferred from the channels to the segments. When the RTM signal becomes logic high, all of the control signals SGS<[0047] 0>, . . . , SGS<N> for conducting the bit lines BL, BLB of the segments to the data transfer line become logic high.
[0048] A BGM signal becomes logic high when a command for data transfer between the segment and the channel. [0048]
[0049] FIG. 9 is a diagram for explaining another embodiment of data transfer between segments and channels in the virtual channel DRAM of the present invention. FIG. 9 is similar to FIG. 1 except that a segment selector [0049] 120 replaces a segment selector 20. The segment selector 120 simultaneously conducts the bit line pair BL, BLB bus in one of the segments to the data transfer line or for selectively conducts the bit line pair BL, BLB bus in the segments to the data transfer line.
[0050] At first, as shown in FIG. 10, the segment selector [0050] 120 is coupled between the bit line pair BL, BLB of the segments and the data transfer line and includes transfer gates, each switched by the control signals SGS<0>, . . . , SGS<N> for selecting one of the segments and an RTM signal.
[0051] The SGS<[0051] 0> signal among the SGS<0>, . . . , SGS<N> that becomes logic high when the bit line BL/BLB bus of the segment<0> block is conducted to the data transfer line becomes logic high. On the contrary, the SGS<N> signal that becomes logic high when the bit line BL/BLB bus of the segment<N> block is conducted to the data transfer line.
[0052] RTM signal becomes logic high in the external command mode for a particular test in which data should be transferred from the channels to the segments. When the RTM signal becomes logic high, the bit lines BL, BLB of the segments are conducted to the data transfer line. [0052]
[0053] In FIG. 9, a number of segments [0053] 10_0 to 10_N for dividing the whole cell conducted to the bit lines BL, BLB by an active command are similar to those as shown in FIG. 2.
[0054] And, in FIG. 9, a plurality of channel selector [0054] 40 for selectively conducting the CRG/CRGB bus in one of the channels to the data transfer line are similar to those as shown in FIG. 4. The CS<0> among the CS<0>, . . . , CS<M> becomes logic high when the CRG/CRGB bus of the channel <0> is conducted to the data transfer line.
[0055] And, in FIG. 9, a number of channels [0055] 50_0 to 50_N for temporarily storing data transferred between the bit lines BL, BLB, the data transfer line and the channel bus line CRG/CRGB are similar to those as shown in FIG. 5.
[0056] And, in FIG. 9, SGS signal generator [0056] 30 for selectively conducting the bit line pair BL, BLB bus in one of the segments to the data transfer line is similar to that as shown in FIG. 6.
[0057] The SA<[0057] 0>, SAB<0>, SA<1>, SAB<1>, . . . , SA<N>, SAB<N> signals are address signals applied from external for selecting the segment. The SA<0> becomes logic high when the address signal determining logic of the SA<0> and the SAB<0> among the address signals is logic high. On the contrary, SAB<0> becomes logic high when the address signal determining logic of the SA<0> and the SAB<0> among the address signals is logic low.
[0058] The SA<K> becomes logic high when the address signal determining logic of the SA<K> and the SAB<K> among the address signals is logic high. On the contrary, the SAB<K> becomes logic high when the address signal determining logic of the SA<K> and the SAB<K> among the address signals is logic low. [0058]
[0059] The SGS<[0059] 0> that becomes logic high when the bit line BL/BLB bus of the segment<0> block is conducted to the data transfer line becomes logic high when SAB<0>, SAB<1>, . . . , SAB<K> signals become logic high. And SGS<N> that becomes logic high when the bit line BL/BLB bus of the segment block of segment <N> block is conducted to the data transfer line becomes logic high when SA<0>, SA<1>, . . . , SA<K> signals become logic high.
[0060] A BGM signal becomes logic high when a command for data transfer between the segment and the channel. [0060]
[0061] As described above, in the conventional virtual channel DRAM, the cell conducted to the bit line pair BL, BLB by the active command is divided into a number blocks and data is transferred between one of the channels and one of the segments. [0061]
[0062] In the virtual channel DRAM of the present invention, data can be transferred between one of the channels and a number of the segments in such a way to reduce test time for a whole chip. [0062]
[0063] While the present invention has been shown and described with respect to the particular embodiments, it will be apparent to those skilled in the art that many changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims. [0063]

权利要求:
Claims (7)
[1" id="US-20010005373-A1-CLM-00001] 1. A virtual channel DRAM comprising:
a number of segments for dividing a cell conducted to bit line by an active command is divided into a number blocks;
a number of segment selecting means for selectively conducting the bit line in one of the segments to a data transfer line;
a number of channels for temporarily storing data transferred among the bit line, the data transfer line and a channel bus line;
a number of channel selecting means for selectively conducting the channel bus line in one of the channels to the data transfer line; and
control signal generating means for generating a first control signal used for selectively conducting the bit line in one of the segments to the data transfer line and used for simultaneously conducting the bit lines of all segments to the data transfer line in a predetermined external command mode.
[2" id="US-20010005373-A1-CLM-00002] 2. The virtual channel DRAM as recited in
claim 1 , wherein the control signal generating means includes:
first even order NAND gates at input stage, to each of which address signals applied from external to select one of the segments and a second control signal;
second odd order NAND gates at input stage, to each of which the address signals applied from external to select one of the segments and the second control signal;
second even order NAND gates at output stage, to each of which outputs of the even order NAND gates at the input stage and a third control signal and each of which provides the first control signal; and
second odd order NAND gates at output stage, to each of which outputs of the odd order NAND gates at the input stage and the third control signal and each of which provides the first control signal.
[3" id="US-20010005373-A1-CLM-00003] 3. The virtual channel DRAM as recited in
claim 2 , wherein the second control signal becomes logic high when a command corresponding to data transfer between the segments and the channels is applied.
[4" id="US-20010005373-A1-CLM-00004] 4. The virtual channel DRAM as recited in
claim 2 , wherein the third control signal becomes logic high in an external command mode for a predetermined test in which data is transferred from the channels to the segments.
[5" id="US-20010005373-A1-CLM-00005] 5. A virtual channel DRAM comprising:
a number of segments for dividing a cell conducted to a bit line by an active command into a number of blocks;
segment selecting means for selectively conducting the bit line in one of the segments to a data transfer line and for selectively conducting the bit lines in all segments to the data transfer line in a predetermined external command mode;
a number of channels for temporarily storing data transferred among the bit line, the data transfer line and a channel bus line;
a number of channel selecting means for selectively conducting the channel bus line in one of the channels to the data transfer line; and
control signal generating means for generating a control signal for selectively conducting the bit line in one of the segments to the data transfer line.
[6" id="US-20010005373-A1-CLM-00006] 6. The virtual channel DRAM as recited in
claim 5 , wherein the segment selecting means includes transfer gates, each coupled between the bit line of each segment and the data transfer line and switched by the control signal selecting one of the segments and a signal, wherein the signal being logic high in an external command mode for a predetermined test in which data should be transferred from the channels to the segments.
[7" id="US-20010005373-A1-CLM-00007] 7. The virtual channel DRAM as recited in
claim 6 , wherein the transfer gates respectively includes NMOS transistors.

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2001-03-08| AS| Assignment|Owner name: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD., KOREA, R Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SONG, DAE-SIK;REEL/FRAME:011581/0370 Effective date: 20001205 |

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2002-08-08| STCF| Information on status: patent grant|Free format text: PATENTED CASE |

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2003-07-15| AS| Assignment|Owner name: INTERNATIONAL WIRE GROUP, INC., MISSOURI Free format text: INTELLECTUAL PROPERTY TERMINATION RELEASE;ASSIGNOR:JPMORGAN CHASE BANK;REEL/FRAME:013804/0142 Effective date: 20030530 |

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优先权:

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申请号 | 申请日 | 专利标题

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KR99-60783||1999-12-23||

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KR1019990060783A|KR100315042B1|1999-12-23|1999-12-23|Virtual channel dram|

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KR1999-60783||1999-12-23||

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